The present invention relates to a reflective active matrix liquid crystal display apparatus applicable to projection liquid crystal display systems.
Reflective projection liquid crystal display systems are used for displaying video data output from computers or storage media, or through communications or broadcasting, etc.
In reflective active matrix liquid crystal display apparatus, pixels consist of reflective pixels electrodes, with transistors and wirings all arranged in layers beneath the reflective pixels electrodes. This structure allows high pixel density, such as, 10 μm or less for pixel pitch, and 0.3 to 0.6 μm for gaps between the reflective pixels electrodes, with no decrease in aperture ratio with a less noticeable aperture structure, for high definition display.
FIG. 1 is a sectional view showing a structure of pixels in a known reflective active matrix liquid crystal display apparatus.
Provided on a well 100 formed in a silicon substrate 110 are transistor areas 15 and capacitance areas 16. Formed in these areas 15 and 16 are a switching transistor Tr and a signal-charging capacitor Cs, respectively, for each pixel.
Pixels are isolated from one another by a field oxide film 112. Also isolated from one another by the film 112 are switching transistors Tr and signal-charging capacitors Cs.
A gate 102 of each switching transistor Tr and an upper electrode 105 of each signal-charging capacitor Cs are made of a polysilicon wiring layer formed on the silicon substrate 110 via an SiO2 insulating layer 109, thus constituting a MIS (Metal Insulator Semiconductor) structure.
A column-signal electrode 101 is wired by a first metal layer formed on an upper layer on the polysilicon wiring layer via an insulating layer 8 so that it is electrically connected to a drain diffusion layer 140, one terminal of each switching transistor Tr, through a via hole C1. Connected to a source diffusion layer 103, another terminal of each transistor Tr, through a via hole C2 is an island-like electrode 104 formed in the first metal layer. The electrode 104 is connected to the electrode 105 of each signal-charging capacitor Cs through a via hole C3.
Formed in the capacitance areas 160 at the silicon substrate side are heavily doped diffusion layers 110 which are connected to one anther by wirings 111 formed in the first metal layer.
The island-like electrode 104 of the first metal layer is formed so that it completely covers the source diffusion layer 103 of the each transistor Tr, thus leaked light cannot reach the layer 103. This light-shielding structure prevents generation of photo carries in a semiconductor body formed in the source well, thus achieving signal-storing and display characteristics which are stable under intense light emission.
Also formed for shielding intense light emission is a shielding pattern 106 made of a second metal layer that is an upper layer on the first metal layer but a lower layer under the uppermost layer in which reflective pixel electrodes 108 are formed. The shielding pattern 106 has an island-like pattern 1002 isolated therefrom by a window 107.
Each pixel electrode 108 and the island-like electrode 104 that is a source wiring for each transistor Tr are connected to each other through a via hole C11, the island-like pattern 1002 and a via hole C10 so that the source diffusion layer 103 of each transistor Tr and the electrode 108 are connected to each other.
An insulating layer 120 that is a lower layer under the pixel electrodes 108 is polished before the electrodes 108 are formed so that its surface becomes optically flat. This is achieved by CMP (Chemical-Mechanical Polish).
A flattening layer 130 is formed to level off a mechanical step in a gap between adjacent pixel electrodes 108, which otherwise cause irregular alignment of liquid crystals and optical scattering, to prevent decrease in display contrast. Such a leveling-off process is, for example, an etch back process in which, after the pixel electrodes 108 are formed, an insulating layer of, for example SiO2, is evenly deposited over the surface of the electrodes 108, and then etch-backed until the surface of the electrodes 108 are exposed.
A light-absorbing layer may be formed on both surfaces of the shielding pattern 106 or a rear surface of each pixel electrode 108 to restrict light multireflection on the second metal layer according to need.
Formed over the upper surface of each pixel electrode 108 is an alignment film 152a for initial molecule alignments of liquid crystal materials in a given direction, thus constituting an active matrix substrate SUB.
An alignment film 152b acting in the same way as the alignment film 152a is formed over the lower surface of a transparent common electrode 13 formed on a transparent substrate 12.
A liquid crystal layer 151 is provided between the active matrix substrate SUB and the transparent substrate 120 so that the alignment films 152a and 152b face each other, to vary incident light in accordance with a signal voltage at the pixel electrodes 108.
The known reflective active matrix liquid crystal display apparatus as described above has high aperture ratio and highly dense pixels.
The applicant of the present invention has developed a ultra-high resolution projection display with about 8 million pixels (3,840 and 2, 048 pixels in horizontal and vertical directions, respectively) for high aperture ratio and pixel density, attributed to the advantages discussed above.
Higher resolution for the known reflective active matrix liquid crystal display apparatus, however, cannot ignore delay characteristics of various drive signals in the apparatus, due to the fact that the higher the number of pixels is, the larger the panel size and the higher the operating frequency is.
FIGS. 2 and 3 illustrate delay of pulses in selection of row-scanning electrodes, which is a first problem for the known liquid crystal display apparatus.
In FIG. 2, row-selection pulses output from a row-scanning electrode driver 6 are transferred based on the characteristics of CR distribution constant circuits constituted by wiring resistors RG, parasitic capacitances Cp and gate capacitances of switching transistors Tr (loads) of row-scanning electrodes G1, . . . , GK, . . . Row-selection pulses become more blunt in waveform and are more delayed as more distant from the driver 6 in a horizontal direction in a pixel area, such as, points A, B, C, and so on.
In the known liquid crystal display apparatus, row-scanning electrodes are made of a polysilicon wiring layer that forms the gate electrodes of the switching transistors Tr. This polysilicon exhibits higher specific resistance, with typical sheet resistance in the order of several ten Ω, than metal wiring materials, such as, aluminum.
Lower resistance for gate wiring layers is usually achieved by forming a silicide layer of, such as W, Ti and Ta, or a Ti-salicide layer on the polysilicon layer. It is however difficult to achieve lower resistance for the polysilicon wiring layer in the same level as the metal wiring layer of aluminum, for example.
Suppose that the above liquid crystal display apparatus having 4, 000 horizontal pixels is fabricated with a pixel pitch of 10 μm.
When a row-scanning electrode wiring is provided by polysilicon having 10 Ω in sheet resistance, a wiring length is 40 mm and wiring resistance is in the range from 200 to 300 kΩ for 1.5-μm wiring width. Gate capacitance C is roughly estimated as 10 pF in combination of gate and wiring capacitances of 4,000 switching transistors Tr.
Under the estimation, delay (bluntness) of row-selection pulses when transferred along a row-scanning electrode is about 1 μsec. in maximum for rising and falling of pulses.
FIG. 3 illustrates various drive signal timings corresponding to the equivalent circuit shown in FIG. 2, illustrating delay in gate selection pulse transfer.
In FIG. 3, voltages VA, VB, VC, . . . , are supplied to column-signal electrodes DA, DB, DC, . . . These voltages are given when display signals are sequentially sampled in horizontal periods at the output of a horizontal-scanning horizontal shift register (not shown).
During a period in which a display signal in a k-th row horizontal period is sampled at a column-signal electrode, a row-selection pulse corresponding to an ON-level of a switching transistor Tr is supplied to a row-scanning electrode at the k-th row from a row-scanning electrode driver (not shown).
When sampling of the display signal in the k-th row horizontal period at all column signal electrodes in this row is finished, which corresponds to a horizontal blanking period just after the k-th row horizontal period (effective signal period), a pulse level from the row-scanning electrode driver is switched to an OFF-level so that the switching transistors Tr in the k-th row are switched from ON to OFF.
The above operation is repeated for each horizontal scanning cycle to sequentially charge display signals to pixels in the succeeding rows.
As described above, signal charge to pixels in each row is achieved by turning off the switching transistors Tr in the row in a horizontal blanking period so that a signal voltage sampled at the row-signal electrode in the row in each horizontal period is set as each pixel voltage.
The signal charge to pixels, however, suffers from delay in transfer of row-selecting pulses depending on the location of pixels at points, such as, the points A, B, C, shown in FIG. 3, having different distances from the row-scanning electrode driver 6, due to the row-selecting pulse delay characteristics discussed with reference to the equivalent circuit shown in FIG. 2.
In FIG. 3, at an operational timing at the point C with a large delay among the three points, a moment at which a row-selection pulse that has an ON-level during the k-th row horizontal effective period and is then switched to an OFF-level to set a pixel potential, overlaps with a display-signal sampling period in the succeeding (k+1)-th row effective horizontal period.
Such an overlap gives pixel voltages affected by an unstable reference voltage, crosstalk on capacitance couplings between circuit components while display signals are being input and sampled during horizontal sampling periods, etc., thus could cause generation of noises, so called streaking, depending on a pattern of displayed images, instability of pixel voltages and intensity, and so on in a horizontal direction.
Such a problem could be solved with horizontal blanking periods long enough between adjacent horizontal periods for a display signal. Longer horizontal blanking periods, however, cause a higher fundamental drive clock rate because pixel addressing is not carried out during horizontal blanking periods.
In the liquid crystal display apparatus having (4,000×2,000) pixels discussed above, for example, flickerless driving at a 120-Hz frame rate gives about 4 μsec. to one horizontal period. The 4-μsec. horizontal period with a 1-μsec. horizontal blanking period results in horizontal effective period/blanking period=3 μsec./1 μsec. with a blanking rate of about 25%. Such a blanking rate raises a horizontal sampling clock rate by about 33% with respect to a non-blanking signal.
A liquid crystal display apparatus having such a large number of pixels discussed above has a very high equivalent dot rate of about 1 GHz, thus operates at a lower operating frequency in the range from 20 to 25 MHz with, for example, parallel 48-phase division of input display signals.
For such a liquid crystal display apparatus, a longer blanking period discussed above is, however, a heavy burden to its liquid crystal display panel and drive system.
Discussed next with reference to FIGS. 4 and 5 is a second problem for the known liquid crystal display apparatus.
FIG. 4 is an equivalent circuit that illustrates delay of a drive signal along wiring in a display-signal sampling circuit included in a column-signal electrode driver connected to a liquid crystal panel 2 in the known liquid crystal display apparatus.
Supplied via an input terminal electrode PDs is a display signal Video that represents several display signals divided in a parallel multi-phase fashion.
The display signal Video is transferred along a common wiring Ls and input to CMOS sampling switches SW1 to SWm. In detail, the display signal Video is transferred based on the characteristics of CR distribution constant circuits each constituted by a wiring resistance Rsig and a wiring parasitic capacitance Csig of the common wiring Ls and an input capacitance of each of the switches SW1 to SWm (loads).
Supplied via an input terminal electrode PDc is a drive clock HCK that represents, for example, two drive clocks.
The drive clock HCK is transferred along a wiring Lc and input to each stage of a horizontal shift register 4a of the column-signal electrode driver. In detail, the drive clock HCK is transferred based on the characteristics of CR distribution constant circuits each constituted by a wiring resistance Rck and a wiring parasitic capacitance Cck of the wiring Lc and an input capacitance of each stage of the shift register 4a (a load).
FIG. 5 illustrates display signal waveforms at input terminals of the CMOS sampling switches SW1 to SWm and their sampling timings. Waveforms WA, WB and WC correspond to the points A, B and C, respectively, indicated in the equivalent circuit shown in FIG. 2, illustrating transfer delay.
FIG. 5 shows that display signals at the input terminals of the CMOS sampling switches have more blunt rising and falling waveforms as more distant from the input terminal electrode PDs.
Reference signs P and Q shown in FIG. 5 indicate timings at which the display signals input to the sampling switches are sampled at the outputs of the shift register 4a of the row-signal electrode driver.
The display signal at the point C (FIG. 4), the most distant from the input terminal electrode PDs, has the most blunt rising and falling waveforms among those at the points A, B and C and at the input terminals of the CMOS sampling switches.
As shown in FIG. 5, the display signal at the point C does not reach the levels of an original input display signal at the sampling timings P and Q, thus suffering from a voltage error ΔV to the original input signal.
As discussed above, the known reflective active matrix liquid crystal display apparatus has a low operating frequency by dividing display signals in a parallel multi-phase fashion.
The known reflective active matrix liquid crystal display apparatus, however, suffers from waveform bluntness for display signals due to the signal transfer characteristics discussed above. Larger waveform bluntness causes generation of double images known as ghosts due to false signals on horizontal pixel locations corresponding to the number of display signals divided in a parallel multi-phase fashion, thus lowering image quality.
Ghost images could be removed by phase adjustments to the display signal Video and the drive clock HCK to the horizontal sift register 4a in FIG. 4. However, waveform bluntness in the direction of wiring due to the characteristics of distribution constant circuits forces highly precise adjustments to phases of the display signal Video and the drive clock HCK, and also transfer delay characteristics in the liquid crystal display panel 2001. Such adjustments restrict design freedom for liquid crystal display panels.
Delay in signal transfer along wrings discussed above could also be eliminated by lowering wiring resistance with a wider wiring width. However, a wider wiring width causes a larger wiring parasitic capacitance.
As discussed above, it is difficult to improve the transfer characteristics of the known reflective active matrix liquid crystal display apparatus.